This application claims the priority of Korean Patent Application No. 10-2003-69039 filed on Oct. 4, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a tape circuit substrate and a semiconductor chip package using the same, capable of meeting the trend towards fine pitch in a semiconductor chip pad.
2. Description of the Related Art
Due to trends toward thin, compact, high integrated, high-speed and high pin count semiconductor devices, tape circuit substrates are increasingly being used in the field of semiconductor chip mounting technology. The tape circuit substrate is configured such that wiring pattern layers and leads connected to the wiring pattern layers are formed on a thin film made of an insulating material such as polyimide resin. TAB (Tape Automated Bonding) technology for collectively bonding the leads of the tape circuit substrate to bumps previously formed on a semiconductor chip can be applied to the tape circuit substrate. Due to these characteristics, the tape circuit substrate is often called a TAB tape.
FIG. 1 is a partial plan view of a general tape circuit substrate.
Referring to FIG. 1, the general tape circuit substrate 100 is configured so that wiring pattern layers 140 are formed on a base film 120 made of an insulating material such as polyimide resin by performing a photoetching process for copper foil laminating. Further, the wiring pattern layers 140 are covered with and protected by a protection film 130 made of solder resist. To achieve electrical connection with a semiconductor chip, inner leads 140a connected to the wiring pattern layers 140 are exposed through the protection film 130 and protrude into a chip mounting portion 110. Here, the chip mounting portion 110 means a portion of the wiring pattern layer 140 where the protection film 130 is not formed for the semiconductor chip mounting.
FIGS. 2 and 3 are partial plan views showing leads of a tape circuit substrate with a semiconductor chip mounted thereon according to a related art.
FIG. 2 shows an in-line lead structure, and FIG. 3 shows a staggered lead structure.
As shown in FIG. 2, in the case of in-line lead structure, leads 210 are exposed through the protection film 130 and protrude side by side in the chip mounting portion 110. Tip ends of the leads 210 are electrically connected with electrode pads 220 of a semiconductor chip 250.
As shown in FIG. 3, in the case of staggered lead structure, leads 260 and 270 are exposed through the protection film 130 and protrude into the chip mounting portion 110. Further, tip ends of the leads 260 and 270 are alternately formed to be different in length so that they can be electrically connected with electronic pads 280 and 290 formed in a zigzag pattern on the semiconductor chip 250.
In other words, FIG. 1 is a schematic view of the TAB tape (tape circuit substrate 100) using the TAB technology, and FIGS. 2 and 3 are enlarged views of a predetermined region 150 of FIG. 1 and show a state where the semiconductor chip 250 is mounted on the tape circuit substrate. As shown in FIG. 1, the tape circuit substrate 100 is configured in such a manner that the leads 140a made of a metal (e.g., Cu) pattern are formed on a surface of the insulating base film 120 made of polyimide or polyester resin. The insulating base film 120 is provided with transport holes 160, which are used in a process of mounting the semiconductor chip on the TAB tape, at opposite side ends thereof along its longitudinal direction. The tip ends of the leads 140a protrude into the chip mounting portion 110 and are arranged in the chip mounting portion so that they can be electrically connected to the electrode pads (not shown) formed on the semiconductor chip.
Referring to FIGS. 2 and 3, the semiconductor chip 250 is first positioned in the chip mounting portion 110 of the tape circuit substrate 100 and the tip ends of the leads 210, 260 and 270 are arranged with, and thermally welded to, the electrode pads 220, 280 and 290 of the semiconductor chip 250, so that the leads 210, 260 and 270 can be electrically connected to the electrode pads 220, 280 and 290. At this time, in the case of in-line leads of FIG. 2, the leads 210 are electrically connected to the electrode pads 220 formed in a row on the semiconductor chip 250. On the contrary, in the case of staggered leads of FIG. 3, the long leads 260 are bonded to the electrode pads 280 positioned near the center of the semiconductor chip 250, whereas the short leads 270 are bonded to the electrode pads 290 positioned near the periphery of the semiconductor chip 250.
However, in the case of in-line leads of FIG. 2, even though intervals between the leads become narrower to cope with the fine pitch trend in the electrode pads of the semiconductor chip according to the recent trend toward thin, compact semiconductor devices, electrode pads whose widths are greater than those of the leads are required in the fundamental manufacturing process and predetermined intervals between the electrode pads are also required for preventing the electrode pads from being short-circuited. Therefore, there is limitation in achieving fine pitch leads.
Furthermore, in the case of staggered leads of FIG. 3, since the electrode pads are arranged in a zigzag pattern, unlike the in-line leads of FIG. 2, the problem of short circuits between electrode pads can be somewhat solved and the average pitch between leads can also be reduced as compared with the in-line leads. However, intervals between the electrode pads 290 of widths generally larger than those of the leads 260 passing by the vicinity of the electrode pads 290 should be kept at a predetermined distance for preventing the possibility of a short circuit between them, so there is also a limitation in implementing or realizing fine pitch leads.